A dynamic logic for verification of synchronous models based on theorem proving

Synchronous model is a type of formal models for modelling and specifying reactive systems. It has great advantage over other real-time that its paradigm supports deterministic concurrent behaviour Various approaches have been utilized verification synchronous based on different techniques, such as checking, SAT/SMT sovling, term rewriting, inference so on. In this paper, we propose approach compositional reasoning rewriting. Specifically, initially variation dynamic logic, called logic (SDL). SDL extends the regular program first-order (FODL) with necessary primitives to capture notion synchrony communication between parallel programs, enriches FODL formulas temporal logical specify safety properties -- mainly concerned in To rightly communications, define constructive semantics SDL. We build sound relatively complete proof system Compared previous approaches, provides divide conquer way analyze verify syntactic structure programs illustrate usefulness SDL, apply small example SyncChart, which shows potential be used practice.